1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same. In particular, the present invention relates to a method of producing a field effect transistor with stable electrical characteristics, and to a semiconductor device obtained by the production method.
2. Description of the Background Art
One example of a method of producing a conventional field effect transistor will be described with reference to xe2x80x9cFUNDAMENTALS OF MODERN VLSI DEVICESxe2x80x9d, ed. YUAN TAUR et al., Cambridge University Press. With reference to FIG. 45, a p-type well 102 and an element isolation film 103, for example, are formed in a silicon substrate 101. Next, a pad oxide film 104 is formed on the silicon substrate 101. Next, a p-type impurity is ion-implanted to form a channel impurity region 116. Thereafter, the pad oxide film 104 is removed.
Next, a polysilicon film (not illustrated) is formed through the intermediary of a silicon oxide film on the silicon substrate 101. A predetermined photoresist pattern (not illustrated) is formed on the polysilicon film. With the use of the photoresist pattern as a mask, the polysilicon film and the silicon oxide film are subjected to anisotropic etching to form a gate insulation film 117 and a gate electrode 118 referring to FIG. 46. With the use of the gate electrode 118 as a mask, an n-type impurity is ion-implanted to form a pair of extension regions 109a, 109b. 
Next, a silicon oxide film (not illustrated) is formed on the silicon substrate 101 so as to cover the gate electrode 118. The entire surface of the silicon oxide film is subjected to anisotropic etching to form side wall silicon oxide films 110 on both side surfaces of the gate electrode 118, as shown in FIG. 47.
Next, referring to FIG. 48, an n-type impurity is ion-implanted with the use of the gate electrode 118 and the side wall silicon oxide film 110 as a mask so as to form a pair of source/drain regions 111a, 111b. 
Next, referring to FIG. 49, cobalt silicide films 112a, 112b, 112c are formed in a sell-aligned manner on the surface of the pair of exposed source/drain regions 111a, 111b and the gate electrode 118. Thereafter, referring to FIG. 50, a silicon oxide film 113 is formed on the silicon substrate 101.
Thus, referring to, FIGS. 51 and 52, a field effect transistor including the gate electrode 118, the extension regions 109a, 109b, and the source/drain regions 111a, 111b is formed on an element formation region partitioned by the element isolation film 103. Here, FIG. 51 illustrates a cross-sectional structure in the gate length direction, and FIG. 52 illustrates a cross-sectional structure in the gate width direction.
However, the conventional method of producing a semiconductor device involves the following problems.
The first one of the problems is a problem accompanying the turn-around, i.e., diffusion of impurities into the extension regions 109a, 109b to a region immediately under the gate electrode 118, reversion conductivity type. Referring to FIG. 46, the pair of extension regions 109a, 109b are formed on the surface of the silicon substrate 101 with the use of the gate electrode 118 as a mask. At this time, the ions serving as the impurity may possibly be implanted to turn around to a region under the gate electrode 118.
Further, referring to FIGS. 53 and 54, by a heat treatment in a process after the, extension regions 109a, 109b are formed, the impurity of the extension regions 109a, 109b is diffused to a region under the gate electrode 118, so that the extension regions 109a, 109b are both extended to the region under the gate electrode 118.
By turn-around (diffusion) of the extension regions 109a, 109b to the region immediately under the gate electrode 118, the effective gate length (a) of the field effect transistor will be shorter. When the gate length becomes less than about 100 nm in accordance with the miniaturization of semiconductor devices, the turn-around of about 10 nm of the extension regions 109a, 109b will be a problem, and the short channel effect deteriorates the electrical characteristics in the field effect transistor, such as increase in the subthreshold current.
Furthermore, referring to FIGS. 53 and 54, the part of the extension regions 109a, 109b formed immediately under the gate electrode 118 and having a comparatively low impurity concentration has a higher electric resistance than the part of the extension regions 109a, 109b located immediately under the side wall dielectric film.
For this reason, the obtained field effect transistor will be equivalent to a field effect transistor in which resistances R are connected in series to the source and the drain, referring to FIG. 55. This makes it hard for the electric current to flow, raising problems such as a slow operation speed.
Next, the second one of the problems is a problem accompanying the rise of impurity concentration in the surface of the channel impurity region 116. In order to meet the miniaturization of field effect transistors, the impurity concentration of the channel impurity region 116 must be raised. The channel impurity region 116 is formed in a step shown in FIG. 45, and the impurity of the channel impurity region 116 will be diffused by a heat treatment in a later-performed process.
In particular, the impurity that diffuses towards the surface of the silicon substrate 101 raises the surface concentration of the channel impurity region 116. Higher surface concentration of the channel impurity region 116 causes rise of the threshold voltage in the field effect transistor.
On the other hand, the semiconductor devices are now designed to have a lower power supply voltage, such as from 5V to 3.3V. In order to meet such a lower power supply voltage, the threshold voltage of the field effect transistor is preferably lower. For this reason, the rise in the threshold voltage of the field effect transistor is against this demand.
Next, the third one of the problems is a problem accompanying the electric field concentration at an end of the element isolation film 103. In order to meet the miniaturization of semiconductor devices, a trench isolation method is employed as an element isolation film 103 for electrically isolating a field effect transistor from other field effect transistors. In the case of an element isolation film 103 formed by the trench isolation method, the electric field of the gate electrode 118 in the neighborhood of the element isolation film 13 is more concentrated than the electric field in the other parts, as shown by B in FIG. 57. By concentration of electric field, a parasitic transistor having a lower threshold voltage is formed in the neighborhood of the element isolation film 103.
In other words, the obtained field effect transistor will be equivalent to a transistor in which the intended transistor T1 is connected in parallel to a parasitic transistor T2, as shown in FIG. 58. Therefore, this parasitic transistor T2 causes the electric current to flow at a lower gate voltage to generate a superfluous leakage current.
Thus, one object of the present invention is to provide a method of producing a semiconductor device that eliminates the aforesaid problems of the prior art and the other object is to provide a semiconductor device obtained by such a production method.
A method of producing a semiconductor device according to one aspect of the present invention is a method of producing a semiconductor device including an impurity region forming step of forming a pair of impurity regions of first conductivity type on a surface of a semiconductor substrate to sandwich a region that is to become a channel region, and an electrode forming step of forming a gate electrode on the region that is to become the channel region, wherein the method includes a removing step and a filling step. The removing step is for removing a surface of the region that is to become the channel region located immediately under the gate electrode as well as a neighboring part thereof, and a part of the impurity region diffused to a region immediately under the gate electrode. The filling step is for filling the removed surface of the region that is to become the channel region as well as the neighboring part thereof and the removed part of the impurity region, with a predetermined film.
According to this method of producing a semiconductor device, a surface of the region that is to become the channel region located immediately under the gate electrode as well as a neighboring part thereof, and a part of the impurity region diffused to a region immediately under the gate electrode are removed, and the removed parts are filled with a predetermined film, whereby the concentration distribution of the impurity immediately under the gate electrode can be controlled. As a result of this, the threshold voltage of a field effect transistor including a pair of impurity regions and a gate electrode can be controlled, whereby a semiconductor device having excellent electrical characteristics can be obtained.
Preferably, the impurity region forming step includes a step of forming a dummy electrode on the region that is to become the channel region, and a step of introducing an impurity of first conductivity type into the surface of the semiconductor substrate with the use of the dummy electrode as a mask; the method includes a step of removing the dummy electrode between the impurity region forming step and the removing step; the filling step includes a step of forming at least a first silicon epitaxial growth layer as the predetermined film; and the electrode forming step includes a step of forming the gate electrode on a region where the dummy electrode has been removed after the filling step.
In this case, a part of the impurity region that diffuses to a region immediately under the gate electrode by a heat treatment is formed in a region immediately under the dummy electrode before forming an intended gate electrode. The intended gate electrode is formed after the diffused part of the impurity region is removed and filled with the first silicon epitaxial growth layer. This can prevent the effective gate length from becoming shorter in the field effect transistor, and also the parasitic resistance can be eliminated.
Preferably, the filing step includes a step of removing a surface of the first silicon epitaxial growth layer as well as a neighboring part thereof, and a step of further growing a second silicon epitaxial growth layer to fill the removed part of the first silicon epitaxial growth layer.
In this case, the impurity concentration of the region where the channel is to be formed can be controlled more precisely by the second silicon epitaxial growth layer located immediately under the gate electrode, and the threshold voltage of the field effect transistor can be lowered, for example, by allowing the impurity concentration of the second silicon epitaxial growth layer to be lower than the impurity concentration of the first silicon epitaxial growth layer.
Preferably, the method includes a step of introducing an impurity of second conductivity type into the surface of the semiconductor substrate for forming the region that is to become the channel region before the impurity region forming step.
In this case, the surface of the region that is to become the channel region and has a higher impurity concentration by diffusion of the impurity of second conductivity type for restraining the short channel effect in the field effect transistor, as well as the neighboring part thereof, are removed, and the removed part is filled with the first silicon epitaxial growth layer, whereby the impurity concentration of the region immediately under the gate electrode can be controlled, and the threshold voltage of the field effect transistor can be controlled.
Preferably, the filling step includes a step of allowing an impurity concentration of the first silicon epitaxial growth layer to be an impurity concentration of second conductivity type lower than an impurity concentration of the region that is to become the channel region, and the removing step includes a step of forming a trench part having a side part which is forwardly tapered along a direction in which the gate electrode extends.
In this case, by forming a forwardly tapered trench, the region that is to become a channel region having a comparatively high impurity concentration remains immediately under the impurity regions. This can restrain the short channel effect of the field effect transistor.
Still preferably, the method includes a step of forming an isolation region for partitioning the pair of impurity regions and the region that is to become the channel region, and the removing step includes a step of forming a trench part having a side part which is forwardly tapered along a direction from a part where the region that is to become the channel region is in contact with the isolation region towards the region that is to become the channel region.
In this case, the region that is to become a channel region having a comparatively high impurity concentration remains in the region immediately under the gate electrode and near the isolation region. This can restrain formation of a parasitic transistor having a lower threshold voltage accompanying the electric field concentration near the isolation region, thereby to reduce the leakage current.
Preferably, the filling step includes a step of forming a silicon epitaxial growth layer containing an element other than silicon, for example, a Group IV element, as the predetermined film before forming the first silicon epitaxial growth layer.
In this case, a strain is generated in the first epitaxial growth layer by the silicon epitaxial growth layer containing an element other than silicon. This improves the mobility of carriers in the first epitaxial growth layer, and the operation speed of the field effect transistor, for example, is improved.
Specifically, it is preferable that the removing step includes a step of forming a trench part having a side surface and a bottom surface, and the filling step includes a step of forming the silicon epitaxial growth layer containing an element other than silicon at least on the bottom surface of the trench part.
Further, it is preferable that the filling step includes a step of forming the silicon epitaxial growth layer containing an element other than silicon only on the bottom surface of the trench part.
In this case, the strain can be uniformly given to the first epitaxial silicon growth layer.
A semiconductor device according to another aspect of the present invention is a semiconductor device including a pair of impurity regions of a predetermined conductivity type, a gate electrode, a first silicon film, and a second silicon film containing an element other than silicon. The pair of impurity regions of a predetermined conductivity type are formed to be spaced apart from each other in a surface of a silicon substrate. The gate electrode is formed through the intermediary of a gate insulation film on a surface of the semiconductor substrate in a region sandwiched by the pair of impurity regions. The first silicon film and the second silicon film containing an element other than silicon are formed only in the region sandwiched by the pair of impurity regions immediately under the gate electrode; the first silicon film is located immediately under the gate electrode; and the second silicon film containing an element other than silicon is located under the first silicon film and gives a strain to the first silicon film.
According to this structure, a strain is generated in the first silicon film by the second silicon film containing an element other than silicon. This improves the mobility of carriers in the first silicon film, and the operation speed and the like of the field effect transistor including a pair of impurity regions and a gate electrode is improved.
Specifically, it is preferable that the element other than silicon that can give a strain to the first silicon film is a Group IV element or an element having a lattice constant different from that of silicon. Such an element can be easily added into the crystals of silicon.
Preferably, the first silicon film is located over an entire surface of the region sandwiched by the pair of impurity regions immediately under the gate electrode.
In this case, the strain can be uniformly given to the first silicon film in which the carriers move.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.